# SpaceFibre

The SpaceFibre IP core supports up to 8 lanes. On the Microchip SmartFusion2 the bit rate is the maximum allowed by the device, 2Gbps per lane (16 Gbps). In the case of the Xilinx Zynq UltraScale+ this rate is 8Gbps per lane (64Gbps total). This IP core comes in 3 different versions. The first one is presented to the processor as a peripheral (AXI/AHB), the second one is a "bare metal" implementation that can be connected to any HDL design without any processor involved or maximum bitrate is needed. The last one is a bus extensor MMAP custom implementation on top of SpaceFibre. For the peripheral flavor, Linux support is available for transmitting raw frames or present it to the OS as a networking interface, supporting TCP/IP.

### Downloads

#### SPECIFICATIONS

| Feature                          | Details                               |
|----------------------------------|---------------------------------------|
| Multilane                        | 1 to 8                               |
| End of packet                    | Yes                                   |
| Packet retransmission on error   | Optional                              |
| Virtual channels                  | No                                    |
| Bitrate                          | 2 Gbps (SF2) 8 Gbps (ZynqMP)         |

#### VERSIONS

This IP core comes in different versions:

**AXI/AXILite:** Ready to connect to an AXI/AXI lite bus. It has an AXI lite slave for configuration and an AXI full interface to read/write data from/to memory

**AHB/APB:** Same concept as AXI/AXILite version but with APB slave for configuration and AHB for memory access

**AxiStream:** Core to be integrated directly to an HDL project without any bus. The maximum bitrate can be achieved in this version

**MMAP:** Custom implementation to extend the bus to another FPGA and use all its peripherals as they were in the same chip.

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